EN0-001 Exam Dumps - ARM Accredited Engineer
Which TWO of the following accurately describe constraints on the location of the Tightly Coupled Memory (TCM) regions in a Cortex-R4 processor? (Choose two)
The Cortex-A9 processor implements a feature called "small loop mode" which reduces power consumption when executing small loops by turning off instruction cache accesses. Which of the following statements describes a condition that must be satisfied for this mode to be enabled?
When an interrupt service routine reads the Generic Interrupt Controller (GIC) Interrupt Acknowledge Register, what state transition occurs for that interrupt ID?
An undefined instruction will cause an Undefined Instruction exception to be taken when:
Processors which implement the ARMv7-A architecture can be configured to allow unaligned memory access. Unaligned accesses have a number of advantages, disadvantages, and limitations.
Which TWO of the following statements are true? (Choose two)
To return from a Data Abort handler and re-execute the aborting instruction, what value should be loaded to the PC?
What are the values of the NZCV bits in the CPSR after executing the following instructions?
LDR R0, = 0xFFFFFFFF
ADDS R0, R0, #1
In a Cortex-A processor, assume an initial value of R1 =0x80004000.
If the following instruction causes a data abort, what value will R1 contain on entry to the abort handler?
LDR R0, [R1, #8]!
When linking with the standard C library, which library functions MUST be redefined in order to port your code to a new piece of production hardware?
An external debugger would need to clean the contents of the processor data cache in which of the following cases?
In which of the following situations would you use a mutex to avoid synchronization problems?
When using an Operating System, which instruction is used by user code to request a service from the kernel?
In a Cortex-A9 processor, when the Memory Management Unit (MMU) is disabled, which of the following statements is TRUE? (VA is the virtual address and PA is the physical address)
Before execution:
R0=0xFFFFFFFF
R1 = ?
EOR R0, R0, R1
If R0=0x00000000 after executing the EOR instruction above, what was the value in R1 before the instruction executed?
The following pair of functions implement a simple mutex spinlock which might be used to protect a critical code section in a multi-threaded application. The address of the lock variable is in r0.
In order to minimize power while waiting for the lock to be available. SEV and WFE instructions can be used to place the processor in a low power state while waiting for the lock to become available. At which points should these instructions be placed?
A simple method of measuring the performance of an application is to record the execution time using the clock on the wall or a wristwatch.
When is this method INAPPROPRIATE?
The Memory Protection Unit (MPU) of Cortex-R4 performs which of the following tasks?
An interrupt handler contains the following instruction sequence at the end. The purpose of these instructions is to clear the interrupt request in the interrupt controller and then safely re-enable interrupts.
STR r0, [r1] ; write to interrupt controller register to clear interrupt request
CPSIE i ; re-enable IRQ interrupts
Which of the following instructions should be placed at position
Which of the following pairs of statements about the difference between a Memory Management Unit (MMU) and a Memory Protection Unit (MPU) is correct?
Which one of these statements is TRUE about code running on final hardware without a debugger attached?
When the software floating point emulation library is used, how will the parameters be passed to the following function?
void foo(float f1, float f2, float f3, float f4);
When programming in C, how many bytes of stack are needed to pass parameters when calling the following function?
int foo( int arg_a, int arg_b, int arg_c )
Which of the following sequences of stages comprise the ARM7TDMI three-stage pipeline?
Which power mode describes the state where the ARM processor is powered down, but its Level 1 caches remain powered?
In an ARMv7-A processor, which control register is used to enable the Memory Management Unit (MMU)?